This invention relates to Cross Connection and switching of digital signals, and more particularly to an optical switching apparatus suitable for switching high-speed digital signals.
An apparatus adapted for effecting digital signal Cross Connection in a large-capacity telephone switching system is described in, for example, "Researches and Developments in Oki Electric", No. 138, (Vol. 55, No. 2), pp. 77-78. The structure of the prior art apparatus is schematically shown in FIG. 1. As seen in FIG. 1, time division switches (TSW) 1 and 3 are combined with a space division switch (SSW) 2 to constitute a Cross Connection for telephone signals and multiplexing apparatus of TST type having a large capacity. The time division switches (TSW) 1 and 3 include a plurality of semiconductor memory switches 10-1 to 10-N and 17-1 to 17-N respectively for effecting telephone cross connection by changing the order of writing and reading data in and from memories. The space division switch (SSW) 2 includes gate switches for effecting telephone cross connection by selecting input signals applied to input ports in every time slot. All of the time division switches (TSW) 1, 3 and the space division switch (SSW) 2 act to process serial digital input signals after converting them into parallel signals so as to decrease the operation speed of the individual memory switches. Therefore, interfaces between the time division switch (TSW) 1 and the space division switch (SSW) 2 and between the space division switch (SSW) 2 and the time division switch (TSW) 3 transmit the digital signals parallel form. Further, cables 4-1 to 4-N connecting the time division switch (TSW) 1 to the space division switch (SSW) 2 and cables 5-1 to 5-N connecting the space division switch (SSW) 2 to the time division switch (TSW) 3 are requred by the number equal to the number of the parallel signals for each of the memory switches 10-1 to 10-N and 17-1 to 17-N. Thus, the prior art apparatus becomes complex in structure and large in scale.
In the prior art apparatus having a complex structure and a large scale as described above, phase matching between individual digital signals is required because serial digital input signals are converted into parallel signals for the purpose of decreasing the operation speed of the apparatus. Thus, the length of the signal transmission cables must be adjusted or buffer memories must be disposed at the signal receiving ends.
Also, when the number of serial-parallel converted signals is large or when the cross connection capacity is large, that is, when the number of the memory switches is large, a serious problem of wiring congestion inevitably arises. In particular, this problem appears at the space division switch (SSW) to which all the signals are concentrated.